1. Field of the Invention
The present invention relates to the field of three-dimensional stacking of semiconductor chips. Embodiments of the present invention provide the opportunity to fully test a TSV-based interconnect while only one of two tiers is under design control of a stack manufacturer.
2. Description of the Related Technology
The semiconductor industry is on an ongoing quest to integrate more functionality into a smaller form factor with increased performance, lower power and reduced cost. Traditionally, only two-dimensional planes were used for this: through conventional CMOS scaling, multiple IP cores in a single die (system-on-chip, SoC), multiple dies in a single package (multi-chip package, MCP) and multiple ICs on a printed circuit board (PCB). More recently, also the third, vertical dimension started to become exploited: system-in-package (SiP), in which multiple naked dies are vertically stacked in a single IC package, and interconnected by means of wire-bonds to the substrate; and package-on-package (PoP), in which multiple packaged chips are vertically stacked.
Three-dimensional (3D) stacking of chips is a hot research item, as it promises higher transistor densities and smaller footprints of electronic products. The latest evolution in this list of innovations is the so-called three-dimensional stacked IC (3D-SIC); a single package containing a vertical stack of naked dies which are interconnected by means of through-substrate-vias (TSVs). 3D stacking based on through-substrate-vias (TSVs) offers the benefits of more functionality, higher bandwidth and performance at smaller sizes, alongside lower power consumption and cost; and this even in an era in which conventional feature-size scaling becomes increasingly difficult and expensive. TSVs provide, as their name indicates, an electrical connection from the active front-side (face) of a semiconductor die through the semiconductor substrate to the back-side. TSVs are conducting nails which stick out of the back-side of a thinned-down die, which allow that die to be vertically interconnected to another die. TSVs are high-density, low-capacity interconnects compared to traditional wire-bonds, and hence allow for much more interconnects between stacked dies, and these interconnects can operate at higher speeds and lower power dissipation. TSVs allow to interconnect multiple vertically stacked dies with each other.
Like all ICs, also these new TSV-based 3D-SICs need to be tested for manufacturing defects, in order to guarantee sufficient outgoing product quality to a customer. Chip stacks should be delivered fault free as much as possible. In 3D chip stacking, the TSVs typically carry all interconnect signals between two dies, and hence are quite critical. Both the TSV manufacturing process, as well as the bonding process are delicate, and hence the TSV-based interconnects are prone to defects, such as for example opens and shorts.
Conventional test solutions include boundary scan testing, and require control and observation of special design-for-test (DfT) features or circuitry. If the dies on both ends of the TSVs are, at design time, under full control of the 3D chip stack designer, special Design-for-Test features can be added to the design of both top and bottom die that allow controllability and observability of the TSV, in order to fully test it. An alternative approach is that both tiers comprise control and/or observe DfT features, whereby the DfT features in the die which is not under control of the stack manufacturer are as desired or expected by the stack manufacturer, either by agreement, by chance, or by standardization. The DfT features in all tiers can be designed to co-operate. Once available, this circuitry reduces the test problem to an interconnect test problem, for which in literature many sets of test patterns are available. An example of a DfT implementation is illustrated in FIG. 1. A first die 10, also called bottom die, is provided with functional TSV connections 11a, 11b. The first die 10 is designed for being connected, via the TSV connections 11a, 11b, to corresponding bond pads 12 on a second die 13, also called top die. Special design for test features 14a, 14b are provided both in the first die 10 and in the second die 13. In the first die 10, a first input port TDI1 is provided for applying electrical input signals to test circuitry 14a for driving TSV connections 11a, and a first output port TDO1 is provided for sensing electrical signals emanating from the TSV connections 11b. A second input port TDI2 is provided for applying electrical input signals to test circuitry 14b for driving TSV connections 11b, and a second output port TDO2 is provided for sensing electrical signals emanating from the TSV connections 11a. Furthermore, a test data select port is provided for applying select signals to multiplexers in the design for test features 14a, 14b. 
Unfortunately it is often the case that one of the dies is not under control of the stack designer, e.g. because it is an already-existing die. Hence the stack designer cannot provide special design-for-test features in the die not under his control, neither can these features be added as an afterthought. Nevertheless, the TSV-based interconnects need to be tested. A particular example thereof is memories, which typically do not have features for boundary scan testing.
Kang et al. disclose, in “8 Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology”, ISSCC'09, Paper 7.2, pp. 130-131, a TSV repair scheme to increase the assembly yield. A number of redundant TSVs is allocated to a group of TSVs. If one of the TSVs fails, it is replaced by one of the redundant TSVs. No distinction is made between regular and redundant TSVs. If a failure occurs at a TSV, the remaining TSVs are all shifted to the neighboring ones, so a failed TSV is always repaired with a neighboring TSV. In order to determine that a TSV fails, a test is needed, but the document does not specify how TSVs are tested.